A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal Fout having a phase that is related to the phase of an input “reference” signal Fref. The PLL is an electronic circuit including a variable frequency oscillator and a phase detector. This circuit compares the phase of the input signal Fref with the phase of a signal derived from an output oscillator and adjusts the frequency of the oscillator to keep the phases matched. The signal from the phase detector is used to control the oscillator in a feedback loop.
Frequency is the time derivative of phase. Keeping the input and output phase in lock step implies keeping the input and output frequencies in lock step. Consequently, a phase-locked loop can track an input frequency, or it can generate a frequency that is a multiple of the input frequency. The former property is used for demodulation, and the latter property is used for indirect frequency synthesis.
A phase detector compares two input signals and produces an error signal, which is proportional to their phase difference. The error signal is then low-pass filtered and used to drive a voltage controlled oscillator (VCO) or a current controlled oscillator (ICO) which creates an output phase. The output is fed through an optional divider back to the input of the system, producing a negative feedback loop. If the output phase drifts, the error signal will increase, driving the VCO phase in the opposite direction so as to reduce the error. Thus the output phase is locked to the phase at the other input. This input is called the reference.
Analog phase-locked loops are generally built with an analog phase detector, a low pass filter and a VCO placed in a negative feedback configuration. A digital phase-locked loop uses a digital phase detector; the digital PLL may also have a divider in the feedback path or in the reference path, or both, in order to make the output signal frequency of the phase-locked loop a rational multiple of the reference frequency. A non-integer multiple of the reference frequency can also be created by replacing the simple divide-by-N counter in the feedback path with a programmable pulse swallowing counter. This technique is usually referred to as a fractional-N synthesizer or fractional-N phase-locked loop. A fractional phase-locked loop can generate a frequency that is a fraction of the input frequency, and such a phase-locked loop, may have uses for various electronic devices such as mobile phones and other portable devices.
The oscillator generates a periodic output signal, and the oscillator is initially assumed to be at nearly the same frequency as the reference signal. If the phase from the oscillator falls behind the phase of the reference, then the phase detector changes the control voltage of the oscillator so that it speeds up. Likewise, if the oscillator phase moves ahead of the reference phase, the phase detector changes the control voltage to slow down the oscillator. Since initially the oscillator may be far from the reference frequency, practical phase detectors may also respond to frequency differences, so as to increase the lock-in range of allowable inputs. Depending on the application, either the output of the controlled oscillator, or the control signal to the oscillator, provides the useful output of the phase-locked loop system.
A typical fixed point Δ-Σ modulator-based fractional-N phase-locked loop is illustrated in FIG. 1. Referring to FIG. 1, the phase-locked loop 100 comprises a phase-frequency detector (PFD) 110, which receives input signal Fref and compares the input signal Fref to a feedback signal from feedback divider 150. The PFD output controls current controlled oscillator (ICO) 140 such that the phase difference between the two inputs is held constant, making it a negative feedback system.
The output of PFD 110 is fed to a charge-pump (CP) 120. A charge pump phase detector 120 may have a dead band where the phases of inputs are close enough that the detector detects no phase error. For this reason, charge pump phase detectors 120 are associated with significant minimum peak-to-peak jitter, because of drift within the dead band. However these types of charge pump phase detectors 120, having outputs consisting of very narrow pulses at lock, are very useful for applications requiring very low VCO spurious outputs. The narrow pulses contain very little energy and are easy to filter out of the VCO control voltage, resulting in low VCO control line ripple and therefore low frequency modulation (“FM”) sidebands on the VCO.
The output of the charge pump 120 is in turn, coupled to a loop filter (LF) 130. The PLL loop filter 130 (usually a low pass filter) generally has two distinct functions. The primary function is to determine loop dynamics, which is also called stability. This loop dynamics determination is how the loop responds to disturbances, such as changes in the reference frequency, changes of the feedback divider, or at startup. Common considerations are the range over which the loop can achieve lock (pull-in range, lock range or capture range), how fast the loop achieves lock (lock time, lock-up time or settling time) and damping behavior. Depending on the application, these considerations may require one or more of the following: a simple proportion (gain or attenuation), an integral (low pass filter), and/or derivative (high pass filter).
The output of the loop filter 130 is fed to a voltage controlled oscillator or current controlled oscillator. In this example, FIG. 1 shows a current-controlled oscillator (ICO) 140. All phase-locked loops employ an oscillator element with variable frequency capability. This oscillator element can be an analog VCO or ICO either driven by analog circuitry in the case of an analog phase-locked loop or driven digitally through the use of a digital-to-analog converter as is the case for some digital phase-locked loop designs.
The output of ICO 140 is fed to the output divider 170, which uses input signal N to control division of the output signal, to produce output signal Fout. PLLs may include a feedback divider 150 between the oscillator and the feedback input to the phase detector to produce a frequency synthesizer. A programmable divider is particularly useful in many applications, since a large number of transmit frequencies can be produced from a single stable, accurate, but expensive, quartz crystal-controlled reference oscillator.
If the feedback divider 150 in the feedback path divides by M and the reference input divider divides by N, it allows the PLL to multiply the reference frequency by M/N in a fractional PLL. It might seem simpler to just feed the PLL a lower frequency, but in some cases, the reference frequency may be constrained by other issues, and then the reference divider is useful.
The feedback is not limited to a frequency divider. This element can be other elements, such as a frequency multiplier, or a mixer. The multiplier will make the VCO/ICO output a sub-multiple (rather than a multiple) of the reference frequency. A mixer can translate the VCO/ICO frequency by a fixed offset. It may also be a combination of these elements. An example being a divider following a mixer, which allows the divider to operate at a much lower frequency than the VCO/ICO without a loss in loop gain.
As illustrated in FIG. 1, the output from ICO 140 is fed back to feedback divider 150. To obtain a fractional output ratio, the divide ratio K of the feedback divider 150 is modulated by a Δ-Σ modulator 160 according to the control input M. The output frequency Fout is related to the input frequency Fref by the expression:
                    Fout        =                              M            N                    ⁢          Fref                                    (        1        )            
FIG. 1 also illustrates some example bit-widths that may be used in a fractional PLL of this type. As can be seen, the feedback divide ratio M, is represented by 6 bits for the integral part and 20 bits for the fractional part in the base-2 (binary) number system. The output divide ratio N, an integer, has been expressed using 6 bits for the integral part only. Hence, there is an inherent limitation on the reference to output frequency ratios that can be obtained using this scheme. This point is illustrated by an example as follows.
For this example, assume the reference frequency Fref is 12 MHz. The output frequency needed is 11.2896 MHz. This output frequency is an actual requirement for a cell phone in order to be able to support a 44.1 kHz×256 (=11.2896 MHz) mode for Time Division Multiplex, Inter-Integrated Sound (TDM/I2S) protocols, and 12 MHz is the clock signal supplied to a typical signal processing chip.
Also assume in this example that the output divide ratio is fixed to 4010, where xxyy, implies a number xx in base yy. In this case, the feedback divide ratio M needed would be 37.63210. This ratio does not seem to be a problem, but when the number 37.63210 is converted to base-2, it yields 100101.10100001110010101100 . . . 2. In other words, it is a non-terminating number in base-2. Moreover, when truncated to 20 or even 30 decimal bits, the resulting number will always have an error when compared to 37.63210. The result would be that the output frequency would be off the target frequency of 11.2896 MHz, and therefore, may lead to synchronization inaccuracy and maybe even to dropped samples when used as the main clock for TDM/I2S data transfers.
Two scenarios may seem as intuitive solutions for increasing the frequency resolution of a fractional PLL. A first approach would be to determine whether there was another value for N that can yield a terminating M. FIG. 2(a) shows the error incurred when representing M using 20 fractional bits. Clearly, there is no value of N which yields zero error in M. A second intuitive approach would be to determine if the number of fractional bits could be increased. FIG. 2(b) shows the errors in M when represented using 30 fractional bits. As can be seen, the error can be made smaller but not removed completely.
Thus, the techniques illustrated in FIGS. 2(a) and 2(b) may be used to minimize the error in the output frequency, however, they fail to eliminate the error entirely. Additionally, even though the problem was demonstrated using these particular exemplary numbers, there are numerous other cases as well which exhibit the same complication. For example, if Fref=12 MHz and Fout=12.288 MHz, which is 48 kHz×256, this example also produces a non-terminating binary number, which when truncated, results in an error in the output frequency.